The present invention concerns an arrangement for transmitting data over a bus having a central unit which initiates data transmission and one or several peripheral units linked to each other by the bus.
An arrangement of this sort is known from the DE-PS 31 33 407. There, a processor as a central unit is connected to a memory as a peripheral unit by a bus. The bus contains data lines whose number corresponds to the word width, address lines for addressing the individual memory cells and control lines for controlling the data transmission. Data transmission can take place selectably as 8-bit-wide byte accesses or 16-bit-wide word accesses. To select the access mode, besides READ and WRITE signals, a BYTE signal is also provided which is evaluated in a control signal decoder. The processor executes a fixed microprogram which is tailored to the special hardware configuration. A change in the number of data lines thus leads necessarily to a change in the microprogram. For example, the memory cannot be easily replaced by a memory of another data width.
In electronic, modularly designed devices in which the components central unit, peripheral unit and bus are interchangeable, there exist both cost-effective devices with a small data bus width as well as devices of the upper class of capacity which are characterized by a data bus of large width.
The underlying object of the invention is to create an arrangement in which the components of different classes of capacity can be combined together in any way.